1. Field
The embodiments relate to high-speed network devices, and more particularly to optimizing memory access for high-speed network devices.
2. Description of the Related Art
Synchronous optical network (SONET) is a standard for optical telecommunications transport formulated by the Exchange Carriers Standards Association (ECSA) for the American National Standards Institute (ANSI), which sets industry standards in the U.S. for telecommunications and other industries. Network processors (NP) are emerging as a core element of network devices, such as high-speed communication routers. NPs are designed specifically for network processing applications.
The unique challenge of network processing is to guarantee and sustain throughput for the worst-case traffic. For instance, the case of the optical level OC-192 (10 Gigabits/sec) POS (Packet over SONET) packet processing presents significant processing and throughput challenges. It requires a throughput of 28 million packets per second or service time of 4.57 microseconds per packet for processing in the worst case. The latency for a single external memory access is much larger than the worst-case service time.
Therefore, modern network processors usually have a highly parallel architecture with non-uniform memory hierarchy. Network processors can consist of multiple microengines (MEs, or programmable processors with packet processing capability) running in parallel. Each ME has its own local memory (LM), for example registers.
Various constraints may be applied to accessing register files, which complicates the management of the register files. For example, a local memory in a NP can be addressed using a BASE-OFFSET word address. The BASE value is stored in a specific base-address register, and there is 3-cycle latency between writing the base-address register when its value changes.
The OFFSET is a constant from 0 to 15. The final address in the BASE-OFFSET mode, however, is computed using a logical OR operation (i.e., BASE|OFFSET). Therefore, to support C pointer arithmetic, e.g., pointer+offset, using the BASE-OFFSET mode of local memory where BASE=pointer and OFFSET=offset, proper alignment of BASE has to be ensured such that the condition in FIG. 1 holds. Otherwise, to access that address, the base-register has to be set to pointer+offset, and the OFFSET is set to 0. FIG. 1 illustrates the alignment requirement of the BASE-OFFSET addressing mode of the local memory.